Typically, a memory comprises an array region and a periphery region. The memory cells in the array region are controlled by conductive lines, such as bit lines and word lines. These conductive lines extend from the array region to the periphery region and are connected to decoders in the periphery region. In the array region, the lines can be formed in a regular environment. However, in the region such as near the boundary, the lines must be formed in a more complicate environment. Such a complicate environment may result in a higher failure rate. For example, in a typical case of 3D vertical gate NAND memory, the fan-out portions of word lines are formed outside stacks of bit lines. In other words, the word lines are fabricated across the boundaries of the bit lines. As such, bridges may occur between the word lines due to the unpredictable lithography or etching behavior in the bit line boundary regions.